A memory cell of semiconductor memory device such as a DRAM (Dynamic Random Access Memory) cell may include a transistor and a storage capacitor. When the size of the memory cell is scaled down to obtain a highly integrated DRAM, the area of a semiconductor substrate occupied by the storage capacitor may be reduced. This may reduce the capacitance of a typical storage capacitor, such as a capacitor having a two-dimensional planar structure.
When the capacitance of a storage capacitor is reduced, the signal/noise (S/N) ratio may be lowered, and soft errors may be caused by alpha (α) particles. Thus, the capacitance of storage capacitors should be maintained at an acceptable level even in highly integrated DRAM cells.
Various approaches have been proposed to increase the capacitance of storage capacitors, including reducing the thickness of the dielectric film, forming the dielectric film of a material having a large dielectric constant, and/or enlarging the operational area of the storage capacitor.
For example, to enlarge the operational area of a storage capacitor, storage capacitor design has evolved from a planar capacitor structure to three-dimensional stack-type and/or trench-type capacitor structures. In the case of stack-type capacitor structures, cylinder-type capacitors and/or fin-type capacitor structures have been developed to increase the area of the storage electrode.
When using a dielectric material having a high dielectric constant, such as, for example, Ta2O5, Al2O3, and/or HfO2, as a dielectric film of storage capacitor, the quality of the interface of the dielectric with a polysilicon electrode may decrease. In particular, the quality of the interface of the dielectric with a polysilicon electrode may decrease as the dielectric constant increases. Also, if the thickness of the dielectric film is reduced, leakage current may increase due to tunneling effects. To control such leakage current, a layer having a low dielectric constant, such as a silicon oxide nitride layer (SiON), may be added between a polysilicon electrode and a dielectric film, but this may result in a decrease of overall capacitance. Thus, it has been proposed to employ, as an electrode, a metal having a high work function, such as TiN, Pt, etc., instead of using a polysilicon electrode.
For example, in a capacitor using Al2O3 or HfO2 as a dielectric film, an MIS (Metal Insulator Silicon) structure has been formed in which polysilicon (poly-Si) is used as a storage electrode (i.e., a lower electrode), and a metal layer is used as a plate electrode (i.e., an upper electrode). In addition, research and development for an MIM (Metal Insulator Metal) structure in which both the storage electrode and the plate electrode include metal layers has been actively pursued.
When a TiN layer having a high work function is used as a storage electrode that is electrically connected with a contact plug formed of a silicon-containing material such as polysilicon, the ohmic contact resistance between the electrode and the contact plug may increase. Thus, a metal silicide layer may be formed between the contact plug and the storage electrode, so as to reduce the ohmic contact resistance therebetween.
A metal silicide layer may serve as an ohmic layer that provides an interface between a silicon substrate and an upper metal layer, or between the storage electrode and a contact plug formed on a silicon substrate. Further, the metal silicide layer may serve as a diffusion barrier layer to prevent diffusion of materials between a metal layer and an underlying semiconductor region, or between two metal layers in a multimetal system.
For example, a metal silicide layer may be formed of TiSi2 or a group VIII silicide (e.g., PtSi2, PdSi2, CoSi2, NiSi2, etc.). In particular, TiSi2 may be used widely in semiconductor devices under the 0.25 μm level.
A known method of manufacturing a capacitor in which TiSi2 is used as a storage electrode is described as follows.
FIGS. 1A to 1H are sectional views illustrating the fabrication of a storage capacitor according to conventional methods.
As shown in FIG. 1A, a first interlayer insulation layer 12 is formed on a semiconductor substrate 10 and/or on a conductive region 11 formed on the semiconductor substrate 10. Portions of the interlayer insulation layer 12 are selectively removed to form a contact hole 13 which exposes portions of the semiconductor substrate 10 and/or the conductive region 11. The conductive region 11, which may be a conductively doped region in the semiconductor substrate 10, may, for example, form a source/drain region of a transistor of a memory cell.
As shown in FIG. 1B, a layer of polysilicon doped with conductive impurities is formed over the face of the semiconductor substrate including the contact hole 13. The polysilicon is partially removed to expose the first interlayer insulation layer 12, thereby forming a contact plug 14 within the contact hole 13.
With reference to FIG. 1C, an etch stop layer 15, a molding oxide layer 16 and a hard mask layer 17 are sequentially formed on the contact plug 14 and the first interlayer insulation layer 12.
Referring to FIG. 1D, a photoresist pattern (not shown) is formed on the hard mask layer 17 and patterned using a photolithography process. Portions of the hard mask layer 17 may be selectively removed using the photoresist pattern as an etch mask. The photoresist pattern is removed, and portions of the molding oxide layer 16 and the etch stop layer 15 are selectively etched using the hard mask layer 17 as an etch mask, to thereby form a recess 18 that exposes the contact plug 14.
As shown in FIG. 1E, a titanium layer 23 and a titanium nitride layer 24 are deposited on the side faces and the lower face of the recess 18 and on an upper part of the molding oxide layer 16 to form a storage electrode 19. Portions of the titanium layer 23 formed on the lower face of the recess 18 in which the contact plug 14 is exposed may react with silicon in the contact plug 14 to form a titanium silicide layer 23a. 
As shown in FIG. 1F, a sacrificial oxide layer 26 is formed to fill the recess 18. The hard mask layer 17 and portions of the sacrificial oxide layer 26 are then removed. For example, the wafer may be planarized by a chemical mechanical polishing (CMP) or an etch-back process, to separate adjacent nodes of the storage electrode 19.
Referring to FIG. 1G, the sacrificial oxide layer 26 and the molding oxide layer 16 formed in the periphery of the storage electrode 19 may be removed, for example, by using an etching solution. The etching solution for removing the sacrificial oxide layer 26 and the molding oxide layer 16 may include a mixed buffer solution of HF and NH4F, e.g., an LAL solution in which HF:NH4F are mixed at a ratio of about 1:6˜1:10. As the buffer solution contains a strong acid such as HF, portions of the titanium layer 23 of the storage electrode 19 exposed in removing the sacrificial oxide layer 26 and the molding oxide layer may also be removed by the buffer solution. Moreover, in removing the sacrificial oxide layer 26 and the molding oxide layer 16, the buffer solution may penetrate through the titanium nitride layer 24, which may cause damage to the titanium silicide layer 23a provided in a lower part of the titanium nitride layer 24 and/or to the contact plug 14.
With reference to FIG. 1H, a dielectric layer 20 and a plate electrode 21 are formed on the storage electrode 19, thus forming a storage capacitor 30. A second interlayer insulation layer (not shown) may be formed to bury the storage capacitor 30.
Some conventional methods of forming a storage capacitor may employ an MIM structure in which a storage electrode 19 and/or a plate electrode 21 is formed of a metal such as titanium and/or titanium nitride. A metal silicide layer may be formed between the contact plug 14 and the storage electrode 19, which may reduce the ohmic resistance between the contact plug 14 and the storage electrode 19.
Conventional methods of forming a storage capacitor may have certain drawbacks, however. For example, in some conventional methods, a buffer solution may penetrate through the titanium nitride layer 24 when removing the sacrificial oxide layer 26 and the molding oxide layer 16, which may cause damage to the titanium silicide layer 23a in a lower part of the titanium nitride layer 24 and/or to the contact plug 14. Such damage may result, for example, in a decrease of the production yield of memory devices incorporating a conventional storage capacitor.